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> LTE  > IP > LTE-eNB

       
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▪ Coverage
- Specification : 3GPP LTE Release 9 (FDD and TDD)
- DL: 300Mbps, UL: 75Mbps
- Antenna Config.: 4 Tx / 2 Rx
- Hardware-MAC with UEA (UMTS Encryption Algorithm) and UIA (UMTS Integrity Algorithm)
- Bandwidth Support : 1.2MHz / 3MHz / 5MHz / 10MHz / 15MHz / 20MHz
▪ Compactness

- DMA engines for MAC/RLC/PDCP Layer
- Hardwired ciphering/parameter calculator in order to lessen CPU load
- Easy multiplexing of HARQ/L2 memory with the system memory (DRAM)
- Fitted in single FPGA with external memory (about 70% occupied on Xilinx V6-550T or Altera S4-530)

▪ Completeness

- Femto to Macro (capable of accommodating up to 1000 RRC CONNECTED users)
- Already Fitted in Altera and Xilinx FPGA
- Using no FPGA-dependent blocks in the design (ready to ASIC)
- Conforming to “LTE eNB L1 API Definition” of Femto Forum

▪ Details on eNB IP
- Easy to Upgrade

# Arithmetic blocks in a type of stand-alone module for eNB and UE
# Ready for going to ASIC
# Mainly using single port RAM for ASIC (much smaller than dual-port RAM)
# Floating and fixed point simulators identical to HW
# Hardware test platform for real-time verification of functionality and performances

 

- Hardware MAC and some engines to lessen S/W load

# Hardware implementation of Ciphering and Parameter-calculating engines
# Hardware MAC processing payload data in TS 36.321/TS 36.322/TS 36.323
# Great efforts made for HW/SW partitioning in order to maintain flexibility


- Turbo Decoder

# 16/8/4 parallel decoders with overlapping
# Wide dynamic range for LLR (10 bits)
# Below 0.1 dB implementation loss


- Multi-User Capabilities

# Adopting ML or MMSE-SIC detection algorithms with SIC
# Adopting floating point scheme for wide dynamic range
# Very compact implementation without any performance loss