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> DESIGN SERVICE  > MODULES

       
modules
modules
platform
design history
 
   
- Samsung ARM920T(S3C2440) CPU
- Single Core/ Max 400MHz Core clock
- Max 32MByte SDRAM / Max 128MByte NOR Flash
- JTAG Interface
- USB 1.1 Full Speed 12Mbps
- Debug UART
+ External Connector Pins
- 16Bit Localbus, Address 12bit, Chip Select x2
- GPIO x 15/ Interrupt x2/ UART x1
- Reset Input
- Cleverlogic bootloader (serial Download)
- 55mm x 35mm
- 3.3V/300mA, Power Input Molex-2p connector
- Samsung ARM920T(S3C2440) CPU
- Single Core/ Max 400MHz Core clock
- Max 256MByte SDRAM / Max 128MByte NOR Flash
- JTAG Interface
- USB 1.1 Full Speed 12Mbps
- Debug UART
+ External Connector Pins
- 32Bit Localbus, Address 24bit, Chip Select x4
- GPIO x24/ Interrupt x8/ UART x3/ SPI x1/ I2C x1
- Reset Input/Output
- Cleverlogic bootloader (serial Download)
- 65mm x 45mm
- 3.3V/400mA, Power Input Molex-2p connector
   
- Samsung ARM1176JZF-S(S3C6410) CPU
- Single Core/ Max 800MHz Core clock
- Max 128MByte SDRAM / Max 64MByte NOR Flash
- JTAG Interface
- USB 2.0 High Speed 480Mbps (Support OTG)
- Debug UART
- Internal CPLD Logic
+ External Connector Pins
- 32Bit Localbus, Address 20bit, Chip Select x4
- GPIO x8/ Interrupt x8/ UART x2/ SPI x1/ I2C x1
- Reset Input/Output
- Cleverlogic bootloader (serial Download)
- 65mm x 45mm
- 3.3V/600mA, Power Input Molex-2p connector
   
- Marvell 88F6281 CPU
- Single Core/ Max 1.5GHz Core clock
- Max 512MByte DDR/ 128MByte NAND
- Giga Ethernet x1
- USB 2.0 High Speed 480Mbps
- Debug UART / JTAG Port
+ External Connector Pins
- MPP Port x30
- PCIex1 x1
- Reset Input
- Linux Kernel 2.6.xx porting/ NAND Booting
- 85mm x 65mm
- 3.3V/3A, Power Input Molex-2p connector
   
- Freescale QorIQ(P2020) CPU
- Dual Core/ Max 1.2GHz Core clock
- Max 1GByte DDR3/ SDCARD
- Giga Ethernet x1
- USB 2.0 High Speed 480Mbps
- Debug UART
+ External Connector Pins
- 16Bit Localbus, Address 28bit, Chip Select x8
- GPIO x14/ Interrupt x7/ UART x2/ SPI x1/ I2C x2
- PCIex1 x2
- Reset Input/Output
- Linux Kernel 2.6.35 porting/ SD Card Booting
- 110mm x 85mm
- 3.3V/3A, Power Input Molex-4p connector
   
- Altera Cyclone III (EP3C5E144) FPGA
- Silicon Labs C8051F020 CPU
- Navsync GPS Receiver module (CW12-TIM)
- Debug UART
+ External Connector Pins
- OCXO 10MHz Output x2
- 1PPS Output
- RS-485 x2/ Uart x2
- 105mm x 60mm
- 5V/2A Power