- ATSC 수신 테스트 시스템
- 10,000,000-gate급 FPGA 2개 장착
  @ FPGA #1
    - LDPC Channel Decoder
  @ FPGA #2
    - 2-layer LDM Deodulator
      # Cloud layer
        - QPSK
        - Symbol rate : 2.2 ~ 2.5Mbps
      # Base layer
        - 64-NUC
        - Symbol rate : 18.2 ~ 18.6Mbps
- Dimension : (H) 70mm X (D) 380mm X (W)230mm
- Center freq. : 400 ~800MHz
- User Interface : RS-232 / MFC 기반 GUI
- DIF(Digital Intermediate frequency) Module 장착
- CleverMPC(Freescale P2020 CPU 내장) Module 장착
- High speed FPGA configuration 지원 CleverACE Module 장착
- 10MHz reference clock output 4-port
- 1Gbit DDR memory 4ea 장착